Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski PDF

By Janusz Rajski

ISBN-10: 3540404481

ISBN-13: 9783540404484

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Extra resources for Arithmetic Built-In Self-Test for Embedded Systems

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19, while the serial outputs of the scan paths drive MISR inputs. The use of multiple scan chains can significantly reduce the test application time. Since the scan paths may be of different lengths, every time a pattern is to be produced, the generator is run for c clock cycles, where c is the size of the longest scan chain. The resultant fault coverage in the STUMPS architectures may not be sat­ isfactory due to the structure of the test generator. If the scan paths are fed directly from adjacent bits of the LFSR, then this very close proximity will cause neighboring scan chains to contain test patterns which are highly corre­ lated.

The spherical patterns are generated by randomly inverting (diffracting) the components of their center cube with probability α. Note that the average Hamming distance between an n-bit center test and its spherical vectors is therefore nα. A realization of the generation process is shown in Fig. 12 [133]. The deterministic cubes are kept in the memory of center vectors and are loaded to the register of center vectors (CVR) prior to their shifting into the scan chain. To produce a set of spherical test vectors around a given center, a random signal is required which is set to 1 with the probability α..

Hence, loading the seed can be performed by resetting the LFSR and shifting the s-bit seed serially, starting with its least significant bit. 3. 11: Decompressor hardware. for each pattern, and can be overwritten between the applications of patterns. Consequently, the LFSR can be implemented by using scan flip-flops. As can be seen in Fig. 11, the scheme requires only one extra feedback (controlled by means of an AND gate) from the scan chain and a multiplexer to allow the seed to be shifted in.

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Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski

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